Description
This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs.
Features of 74LS74:
- Dual D Flip Flop Package IC.
- Operating Voltage: 2V to 15V.
- Propagation Delay: 40nS.
- Minimum High-Level Input Voltage: 2 V.
- Maximum Low-Level Input Voltage: 0.8V.
- Operating Temperature: 0 to 70 C.
- High-Level Output Current: 8mA.
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